This invention relates to active matrix devices and is concerned more particularly, but not exclusively, with driver circuits for active matrix liquid crystal displays (AMLCD""s).
The invention can be applied, for example, to driver circuits of AMLCD""s to be implemented in separate large scale integration (LSI) driver chips, or to be integrated on the display substrate in the form of thin film transistors (TFT) using silicon-on-insulator (SOI) technology. Furthermore the invention can be applied to analogue displays which are supplied with analogue RGB video data, or to digital displays which contain digital-to-analogue (D/A) converters and which have a completely digital interface.
FIG. 1 shows a typical AMLCD 1 composed of N rows and M columns of pixels addressable by scan lines 2 connected to a scan line driver circuit 3 and data lines 4 connected to a data line driver circuit 5. Data voltages are applied to the data lines 4 by the data line driver circuit 5 and scan voltages are applied to the scan lines 2 by the scan line driver circuit 3 so that such voltages in combination serve to apply analogue data voltages to the pixel electrodes 6 in order to control the optical transmission states of the pixels along each row as the rows are scanned in a cyclically repeating sequence. This is achieved as follows for a single row of pixels. The data line driver circuit 5 reads a line of data to be displayed by the row of pixels and applies corresponding data voltages to the data lines 4 so as to charge up each data line 4 to the required data voltage. The scan line 2 corresponding to the row of pixels to be controlled is activated by the application of the scan voltage by the scan line driver circuit 3 so that a TFT 7 associated with each pixel is switched on to transfer charge from the corresponding data line 4 to a pixel storage capacitance 8 (as shown in broken lines in the figure) associated with the pixel. When the scan voltage is removed the TFT 7 isolates the pixel storage capacitance 8 from the data line 4 so that the optical transmission state of the pixel corresponds to the voltage across the pixel storage capacitance 8 until the pixel is refreshed during the next scanning frame. The rows of pixels are refreshed one at a time until all the rows have been refreshed to complete refreshing of a frame of display data. The process is then repeated for the next frame of data.
In the case of analogue displays, the display data is supplied to the data line driver circuit in the form of an analogue video (AVIDEO) signal which is sampled at a frequency dependent on the resolution and frame rate of the display, the sampling frequency (also referred to as the pixel data rate) being equal to fNM where f is the frame rate of the display.
For analogue displays of small size or low pixel resolution, a point-at-a-time data line driver circuit 10 is commonly employed for the data line driver circuit, as shown in FIG. 2. In this circuit 10 a sampling shift register 11 composed of a chain of D-type flip-flops is connected so that the output of each flip-flop controls the gate of an associated sampling transistor 12 for applying the AVIDEO signal to the corresponding data line 4 with its associated parasitic capacitance shown in broken lines at 13 in the figure. The key feature of such a point-at-a-time driving scheme is that the sampling transistors 12 are directly connected to the data lines 4. In operation frame and line synchronisation pulses VSYNC (not shown) and HSYNC indicate the start of a frame period and a line period respectively, and a clock signal CK at the sampling frequency is applied to the clock inputs of the flip-flops so that a circulating xe2x80x9c1xe2x80x9d state within the shift register sequentially activates the sampling transistors 12 at the sampling frequency. The RC time constant formed by the resistance of the sampling transistor 12 and the data line 4 (which may have a resistance of several thousand Ohms). and the distributed capacitance of the data line (which may amount in total to tens of picofarads) must be sufficiently less than the available sampling period (1/fNM) for the sampling to be executed successfully.
FIG. 3 is a timing diagram showing the timing of the signals associated with such a point-at-a-time data line driver circuit, where S1, S2 and S3 refer to the scan voltages applied to the first three scan lines numbered from the top of the display. It will be noted that the AVIDEO signal is sampled at the same time as application of the data voltages to the pixels on activation of the scan lines in successive scanning line periods T1, T2 . . . by the scan voltages S1, S2, S3, such scan voltages being synchronised by the HSYNC pulses. However, since the TFT associated with each pixel of the row is turned on while the data for that row is being sampled onto the data lines 4, the pixels towards the right hand side of the display will be charged with the sampled voltage over an effective scan time which is much less than the line period. Indeed, in the worst case, the effective scan time may be little more than the HSYNC pulse period.
For analogue displays of large size or high pixel resolution, the data lines will be both more capacitative and more resistive so that the available sampling period (1/fNM) is too small for the sampling transistor to charge up the data line directly, and the sampling must therefore be buffered. For analogue displays, a small capacitor, which can be charged or discharged very quickly, can be located within each column of the data drive circuit so as to store samples of the AVIDEO signal. The data voltage can then be transferred to each data line by a buffer circuit. However this transfer operation may take several microseconds and this again puts constraints on the time available to scan the right hand side pixels of the display.
FIG. 4 shows at (a) a typical analogue line-at-a-time data line driver circuit 20 such as is more commonly used for buffered sampling, the circuit 20 comprising a sampling shift register 11 comprising a chain of D-type flip-flops as before, but with the outputs of the flip-flops connected to sampling circuits comprising two sets of capacitative memory elements 21 and 22 and line drivers 23 for driving the data lines. FIG. 4 shows at (b) and (c) two alternative circuit arrangements for such a data line driver circuit 20 in which the two sets of memory elements comprise two capacitors 25, 26 or 27, 28 and associated switches 25A, 26A, or 27A, 27B, 28A, 28B for each data line and the line drivers comprise a buffer 29 or 30 for each data line, as will be described in more detail below.
FIG. 5 shows a timing circuit for such a line-at-a-time data line driver circuit for comparison with the timing circuit of the point-at-a-time data line driver circuit of FIG. 3. The important feature of the line-at-a-time driving scheme is that the scan line is activated only after a complete line of data has been sampled during a line period T1, the next complete line period T2 being used for scanning of the data to the pixels as well as sampling of the data for the next row of pixels. Because sampling and data line driving cannot occur simultaneously, each sampling circuit includes two sets of memory elements 21 and 22 as shown in FIG. 4(a). In the first circuit arrangement of FIG. 4(b), each capacitor 25 is used for sampling a corresponding point in a line of data and its charge is then shared with the capacitor 26. The capacitor 26 and buffer 29 are then used to drive the data line, leaving the capacitor 25 free to sample a corresponding point in the next line of data. In the second circuit arrangement of FIG. 4(c), on the other hand, the capacitor 27 is used for sampling a corresponding point in a line of data while the capacitor 28 and buffer 30 are driving the data line. During the next line period,. the capacitor 27 and the buffer 30 are used to drive the data line while the capacitor 28 is being used for the next line sample. In both these cases two whole lines of video data are stored in analogue memory at any one instant. However this single-line pipeline incurs a significant overhead both in terms of number of components and control circuit complexity.
In the case of digital displays, the data line driver circuits normally use a line-at-a-time driving scheme so that it is necessary to use line memories, usually based on latches. A typical digital data line driver circuit comprises an input register to which digital video data is supplied, for example in 6 or 8 bit RGB format, a storage register in the form of digital latches, and digital-to-analogue (D/A) converters connected to the outputs. of the storage register and supplied with reference voltages for applying data to up to 24 parallel digital data lines by way of output buffers. As the digital data bits are supplied to the input register, they are stored in the register and, when a whole line of data has been stored, the contents of the input register are transferred to the storage register in order to control the D/A converters. In the case of small screen displays, the D/A converters may be connected directly to the data lines so as to charge the data lines by simple charge sharing, although output buffers are required for higher performance displays. The D/A converters most commonly used are parallel converters (such as are referred to by Y. Matsueda, S. Inoue, S. Takenaka, T. Ozawa, S. Fujikawa, T. Nakazawa and H. Ohshima, xe2x80x9cLow-temperature poly-Si TFT-LCD with integrated 6-bit digital data driversxe2x80x9d, Society for Information Display 96 Digest, pages 21-24) and ramp converters. However the digital line memory required for such a circuit is difficult to achieve with SOI digital driver integration.
It is known to use two scan line driver circuits to charge up the same scan line, as disclosed in C. Reita, xe2x80x9cIntegrated driver circuits for active matrix liquid crystal displaysxe2x80x9d, Displays 1993, Vol. 14(2), pages 104-114, and R. Martin, T. Chuang, H. Steemers, R. Fulks, S. Stuber, D. Lee, M. Young, J. Ho, M. Nguyen, W. Meuli, T. Fiske, R. Bruce, V. Da Costa, R. Kowalski, A. Lewis, W. Turner, M. Thompson, M. Tilton and L. Silverstein, xe2x80x9cThe electronic document display: A 6.3-million-pixel AMLCDxe2x80x9d, Journal of the Society for Information Display 1996, Vol. 4(2), pages 65-73, for example. There are two advantages to such a driving scheme which are particularly relevant to circuits which are integrated on the same substrate as the display. The first advantage is that the circuit is rendered more tolerant to faults. The second advantage is that two scan line buffers can be used to charge up the significant capacitance of the scan line and connected TFT""s more quickly and evenly. Furthermore it is known for the scan lines to be physically split down the centre of the display so that the display consists of two display parts which are scanned by separate scan line driver circuits connected to opposite edges of the display. Such an arrangement can be effected on a substrate which is common to the two display parts, or alternatively the display parts may be constituted by two display substrates which are bonded together edge to edge to make a larger area display. In both cases the scan lines of both display parts are controlled so that the same line is activated in the two parts at the same time.
U.S. Pat. No. 4,830,466 discloses an AMLCD 32 in which the scan lines are split down the centre of the display into left and right hand scan line parts 33 and 34 as shown in FIG. 6. The scan line parts 33, 34 are activated in one line period of a point-at-a-time driving scheme, in which the left hand scan line part 33 is activated during the first half of the line period and the right hand scan line part 34 is activated during the second half of the line period. This allows more time for charging of the pixels by the data line driver circuit 37 towards the right hand side of the display as compared with a conventional point-at-a-time driving scheme as described above with reference to FIG. 3. It is to be noted that the two scan line parts 33 and 34 are scanned in a single scanning operation in which a line of data is read and applied to the data lines during application of the scan voltage, but in which the left and right hand scan lines are independently controlled.
It is an object of the invention to provide a novel active matrix device which is applicable to both analogue and digital displays and which ensures driving of the display in an efficient manner without undue circuit complexity.
According to the present invention there is provided an active matrix device comprising a plurality of data lines, a plurality of scan lines, an active matrix of control elements arranged in rows and disposed at intersections of the data lines and scan lines and having data inputs connected to the data lines and scan inputs connected to the scan lines such that each control element is addressable by a combination of data and scan signals applied to a corresponding one of the data lines and a corresponding one of the scan lines, and addressing means for addressing the rows of control elements in successive line periods in response to an input signal, the addressing means comprising data line driver circuit means for sampling the input signal to produce data signals for each of the rows of control elements in a corresponding line period and for applying said data signals to the data lines, and scan line driver circuit means for addressing the scan lines sequentially by applying a scan signal to the scan inputs of the control elements along each of the rows so as to supply said data signals applied to the data lines to the control elements along said row on receipt of said scan signal by the control elements, wherein the addressing means comprises first actuating means for sampling and storing the input signal to produce data signals for a first group of the control elements along said row in a first subperiod of said one line period and for supplying said data signals to the first group of control elements in a second subperiod of said one line period, and second actuating means for sampling and storing the input signal to produce data signals for a second group of control elements along said row in a subperiod which is at least partly coextensive with the second subperiod and for supplying said data signals to the second group of control elements in a subsequent subperiod.
Such an arrangement provides a number of significant advantages as compared with an arrangement utilising a conventional line-at-a-time driving scheme as described above with reference to FIGS. 4 and 5. These advantages render the arrangement particularly applicable to monolithic driver circuits for liquid crystal display devices in which the driver circuits are implemented on the same substrate as the display. The most significant advantage of such an arrangement is that it enables the data line driver circuit means to be implemented utilising only a single data memory for each data line. This is because, instead of the requirement of simultaneous storage for sampling and for driving of the conventional line-at-a-time driving scheme, the same data memory may be used for both sampling and driving in such a part-line-at-a-time driving scheme. It will be appreciated that this provides a significant reduction in the number of components and the circuit complexity of the data line driver circuit means. Furthermore such an arrangement is particularly advantageous when it is applied to digital data drive architectures since the area and power consumption overheads are dramatically reduced. A smaller number of components also increases the yield obtained in fabrication of the device. When applied to analogue data drive architectures, the arrangement is able to offer greater precision in operation than conventional analogue line-at-a-time driving schemes where accuracy is lost by transferring charge from one capacitative memory element to another capacitative memory element, or because of minor mismatches of the capacitative memory elements within a column driver.
In one embodiment of the invention the data line driver circuit means comprises first and second driving means, the first actuating means comprises first switching means for isolating the first driving means from the first group of control elements in the first subperiod and for coupling the first driving means to the first group of control elements in the second subperiod, and the second actuating means comprises second switching means for isolating the second driving means from the second group of control elements in the second subperiod and for coupling the second driving means to the second group of control elements in said subsequent subperiod. This may be referred to as a switchable data line bank driving scheme.
In an alternative embodiment the scan lines comprise first and second separately addressable scan line parts, the first actuating means comprises first scanning means of the scan line driver circuit means for applying a first scan signal to the first scan line part to supply said data signals to the first group of control elements in the second subperiod, and the second actuating means comprises second scanning means of the scan line driver circuit means for applying a second scan signal to the second scan line part to apply said data signals to the second group of control elements in said subsequent subperiod. This may be referred to as a split scan line driving scheme.
Such a split scan line driving scheme presents a number of advantages as compared with conventional line-at-a-time driving schemes as described above with reference to FIGS. 4 and 5. Firstly, because the scan lines are shorter, they are less likely to snap or kink. Also the capacitative loading which the scan lines present to the scan line buffers is substantially decreased, and accordingly the scan line buffers can be made smaller. Alternatively, if the buffer drive capability is maintained, the RC time constant of the line can be increased with no loss in system perforrmance. The scan lines can therefore be made narrower, thus improving pixel aperture ratio in the case of a display device.